When printing electronic features using inkjet printing, the width of printed lines of the features often impacts the performance of the resulting device. In thin-film-transistors (TFTs), the line width of conductors impacts the size and parasitic capacitances of the transistor. High capacitances, e.g. gate-source or gate-drain capacitances, negatively impact the switching speed of TFTs. In active-matrix pixel circuits, high parasitic capacitances can lead to high feedthrough voltages. Moreover, in pixel circuits, the fill-factor of a pixel is negatively affected by wide data bus lines.
It is thus advantageous to minimize the width of printed lines in such environments. However, the line width is usually determined by the ejected fluid, the aperture of the print head nozzle and the applied waveform (in the case of a piezo-electric print head)—all of which have a practical limit of adjustment. So, the lines can only be minimized to a limited degree—which may not be sufficient for some applications.
More particularly, FIG. 1 shows an illustration of a conventional printed TFT 10 (bottom-gate configuration in cross-section). A source 12, gate 14, drain 16, gate dielectric 17 and semiconductor 18 comprise the transistor 10—which is formed on a substrate 20.
As shown, the width of the gate 14 is fixed (determined by the printing process) and, thus, is a limitation on the configuration. The source 12 and drain 16 have a certain overlap 13, 15 with the gate 14. Since a small channel width is generally desirable, this overlap 13, 15 can be large, causing significant parasitic capacitance.
An active-matrix pixel circuit 30 is shown in FIG. 2. As shown, jet-printed features, such as data (or source) line(s) 32 and gate line(s) 34 are limited by the size (e.g. width) of the printed lines. Also, FIG. 2 clearly shows that the fill-factor (area of the drain or pixel pad(s) 36 divided by the total pixel area) in such pixel circuits is limited by the width of the printed lines. In an embodiment such as that shown in FIG. 2, a typical pixel pitch may be approximately 680 microns with 60 micron wide data and gate lines, resulting in a fill factor of about 70%. For smaller pixel sizes the fill factor decreases, which is a problem. A high fill-factor is desirable for image sensors and displays. For example, wide data lines, such as data lines 32, pose a problem in displays because the varying voltage potential on the data lines can affect the display media and degrade the image. Moreover, the overlap of the gate lines, such as gate line 34, with pixel pads, such as pixel pad 36, can cause a substantial feedthrough voltage. As noted in connection with FIG. 1, a large overlap of the source and drain with the gate in a TFT is generally undesirable because of the parasitic capacitance.